[Paper] Sparse Axonal and Dendritic Delays Enable Competitive SNNs for Keyword Classification

Source: arXiv - 2602.09746v1

Overview

This paper demonstrates that learning only axonal or dendritic transmission delays—instead of full synaptic‑delay matrices—lets deep feed‑forward spiking neural networks (SNNs) achieve state‑of‑the‑art accuracy on keyword‑spotting tasks while using far less memory and compute. The authors show that a tiny fraction of active delays (≈20 %) is enough to retain performance, opening a path to lightweight, real‑time SNNs for edge devices.

Key Contributions

• Sparse axonal/dendritic delay learning: Introduces two minimalistic delay mechanisms (axon‑side or dendrite‑side) that replace the dense synaptic‑delay tables used in prior work.
• Competitive accuracy: Achieves 95.58 % on Google Speech Command (GSC) and 80.97 % on Spiking Speech Command (SSC), matching or surpassing the best published synaptic‑delay SNNs.
• Resource efficiency: Reduces memory footprint and buffering latency by up to 80 % compared with full synaptic‑delay models.
• Robustness to sparsity: Shows that performance degrades gracefully when only 20 % of the delays remain active, confirming that most delays are redundant.
• Open‑source implementation: Provides a ready‑to‑run PyTorch‑based codebase for reproducibility and rapid prototyping.

Methodology

1. Network architecture – A conventional deep feed‑forward SNN built from leaky integrate‑and‑fire (LIF) neurons. The only novelty lies in where the learnable delay is placed:
   • Axonal delay – added after the spike leaves the presynaptic neuron, before it reaches the postsynaptic membrane.
   • Dendritic delay – added just before the spike is integrated on the postsynaptic side.
2. Delay parameterization – Each connection carries a single scalar delay (in discrete time steps). During training, these delays are treated as continuous variables and optimized via surrogate‑gradient backpropagation, the same technique used for synaptic weight learning in SNNs.
3. Sparsity enforcement – An L1‑regularizer (or hard thresholding) encourages many delays to collapse to zero, yielding a sparse delay matrix.
4. Training pipeline – Standard data augmentation for speech commands, spike‑encoding via a filter‑bank front‑end, and Adam optimizer with learning‑rate schedules. The loss is cross‑entropy on the final read‑out layer.
5. Baseline comparison – The authors re‑implemented the leading synaptic‑delay SNN and tuned its hyper‑parameters to ensure a fair head‑to‑head comparison.

Results & Findings

• Memory & latency: Axonal delays need only a single‑step buffer per neuron, whereas synaptic delays require per‑connection buffers proportional to the maximum delay value. This translates to ~5‑10× less RAM on typical neuromorphic hardware.
• Sparsity effect: With only 20 % of delays active, accuracy drops by <1 % (GSC) and <2 % (SSC), confirming that most delays are redundant for the task.
• Training stability: Both delay types converge in a comparable number of epochs to synaptic‑delay models, showing that the simpler parameterization does not hinder learning dynamics.

Practical Implications

• Edge AI & low‑power devices – The reduced memory and buffering requirements make these SNNs attractive for microcontrollers, ASIC neuromorphic chips, or FPGA implementations where SRAM is scarce.
• Real‑time keyword spotting – High accuracy combined with low latency (single‑step axonal buffers) enables on‑device wake‑word detection without cloud connectivity, preserving user privacy.
• Simplified hardware design – Implementing a single delay per connection (instead of a delay line per synapse) eases routing and timing constraints, potentially lowering silicon area and power consumption.
• Transferability – The same delay‑learning principle can be applied to other temporal tasks (e.g., gesture recognition, event‑based vision) where timing carries semantic information.

Limitations & Future Work

• Task scope – Experiments focus on keyword classification; broader benchmarks (e.g., speech‑to‑text, continuous audio streams) remain to be tested.
• Delay granularity – Delays are quantized to integer time steps; sub‑step precision could further improve performance but would complicate hardware mapping.
• Hardware validation – The paper reports simulated resource savings; a full silicon or FPGA prototype would be needed to confirm real‑world gains.
• Biological plausibility – While inspired by axonal/dendritic propagation, the model abstracts away many neuro‑physiological details; future work could explore more biologically faithful dynamics.

The authors promise to release their code on GitHub, making it easy for developers to experiment with axonal and dendritic delay learning in their own SNN projects.

Authors

• Younes Bouhadjar
• Emre Neftci

Paper Information

• arXiv ID: 2602.09746v1
• Categories: cs.NE
• Published: February 10, 2026
• PDF: Download PDF