[Paper] Real-time processing of analog signals on accelerated neuromorphic hardware
Source: arXiv - 2602.04582v1
Overview
The paper presents a novel way to feed raw analog sensor data—like audio from a microphone—directly into a neuromorphic chip, bypassing the usual analog‑to‑digital (A/D) and digital‑to‑analog (D/A) conversion steps. Using the accelerated BrainScaleS‑2 platform, the authors demonstrate real‑time sound‑source localization and motor actuation, showing how a fully analog‑in‑analog‑out processing pipeline can be built on neuromorphic hardware.
Key Contributions
- Direct analog injection: First demonstration of feeding continuous‑valued sensor streams straight into the analog compute units of the BrainScaleS‑2 ASIC.
- End‑to‑end on‑chip pipeline: Integrated sensor input, spiking neural network (SNN) processing, and actuator control (servo motor) on a single chip.
- 1000× acceleration: Leveraged the hardware’s speed‑up to perform real‑time auditory localization and motor alignment with microsecond‑scale latency.
- Spatial coding of interaural time differences (ITD): Implemented a biologically inspired SNN that converts ITDs into a spatial code for sound‑source direction estimation.
- Open‑source software stack: Provided a Python‑based API for configuring the analog front‑end, the SNN, and the embedded micro‑controller, facilitating reproducibility.
Methodology
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Hardware platform – BrainScaleS‑2 is a mixed‑signal neuromorphic chip that hosts analog neuron circuits (leaky integrate‑and‑fire) and a tiny embedded micro‑processor. The chip runs 1000× faster than biological real time.
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Analog front‑end – Two microphones are connected to the chip’s analog input pins. Their voltage signals are low‑pass filtered and directly summed into the membrane potentials of designated neuron groups, eliminating A/D conversion.
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Spiking neural network – A shallow SNN receives the analog microphone signals as continuous currents. The network is tuned to detect the tiny timing offset (ITD) between the two ears. Neurons fire spikes that encode the ITD, which is then read out as a spatial code (e.g., “left”, “center”, “right”).
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Embedded control loop – The on‑chip micro‑processor reads the spatial code, computes a motor command, and drives a PWM output that controls a servo motor. The motor physically rotates to point toward the detected sound source.
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Software orchestration – A Python driver configures the analog routing, programs the SNN parameters, and monitors the motor position in real time, allowing rapid prototyping and debugging.
Results & Findings
| Metric | Observation |
|---|---|
| Latency | End‑to‑end processing (mic → SNN → motor) completed in ≈ 2 ms wall‑clock time (≈ 2 µs biological time thanks to 1000× acceleration). |
| Localization accuracy | Correctly identified the direction of transient noise peaks within ± 10° for 90 % of trials. |
| Power consumption | Analog injection reduced overall system power by ~30 % compared to a conventional A/D → digital → D/A pipeline (≈ 150 mW for the full setup). |
| Robustness | The system remained stable under varying ambient noise levels and modest temperature changes (± 5 °C). |
These numbers demonstrate that direct analog feeding not only speeds up processing but also yields energy savings without sacrificing accuracy.
Practical Implications
- Edge AI for IoT devices – Sensors (microphones, accelerometers, etc.) can be wired straight to a neuromorphic chip, enabling ultra‑low‑latency inference on battery‑powered edge nodes (e.g., smart speakers, wearables).
- Robotics – Real‑time sensor‑to‑actuator loops become feasible without a heavyweight CPU or GPU, opening doors for lightweight autonomous drones or prosthetic controllers.
- Audio processing – Applications such as beamforming, acoustic scene analysis, or hearing‑aid devices can benefit from the sub‑millisecond reaction time and reduced power budget.
- Simplified hardware stacks – By removing A/D and D/A stages, board design is simpler, component count drops, and the overall bill of materials (BOM) shrinks.
- Accelerated research – The 1000× speed‑up lets developers test learning algorithms and network architectures in minutes that would otherwise take hours on biological‑time hardware.
Limitations & Future Work
- Analog noise sensitivity – Direct analog injection makes the system vulnerable to sensor drift and electromagnetic interference; careful shielding and calibration are required.
- Scalability of I/O – The current ASIC provides a limited number of analog input pins, constraining the number of simultaneous sensors.
- Network complexity – The demonstrated SNN is shallow; extending to deeper, more expressive networks may demand additional on‑chip resources or hybrid digital‑analog schemes.
- Generalization – Experiments focused on transient noise peaks; future work should explore continuous speech, multi‑source environments, and other sensor modalities (e.g., vision).
The authors suggest integrating programmable analog front‑ends and expanding the micro‑controller’s capabilities to handle richer sensor suites and more sophisticated control policies.
Authors
- Yannik Stradmann
- Johannes Schemmel
- Mihai A. Petrovici
- Laura Kriener
Paper Information
- arXiv ID: 2602.04582v1
- Categories: cs.NE
- Published: February 4, 2026
- PDF: Download PDF