[Paper] A Compute and Communication Runtime Model for Loihi 2

Source: arXiv - 2601.10035v1

Overview

Intel’s Loihi 2 is one of the first commercially‑available neuromorphic chips, promising massive speed‑ups and energy savings for workloads that can exploit its asynchronous, compute‑in‑memory fabric. However, developers have little guidance on how long a given algorithm will actually run on the hardware, especially when communication across the on‑chip network becomes a bottleneck. This paper introduces the first max‑affine (multi‑dimensional roofline) runtime model for Loihi 2 that jointly captures compute and communication costs, and validates it against real measurements on matrix‑vector multiplication and a QUBO solver.

Key Contributions

• A lower‑bound, max‑affine runtime model that extends the classic roofline concept to include both compute and NoC (Network‑on‑Chip) communication on Loihi 2.
• Microbenchmark suite that characterizes per‑core compute throughput, packet latency, and congestion behavior, feeding directly into the model parameters.
• Empirical validation showing Pearson correlation ≥ 0.97 between predicted and observed runtimes for two representative kernels (linear layer and QUBO solver).
• Analytical scalability analysis that derives closed‑form expressions for communication‑bound regimes, exposing an area‑runtime trade‑off for different spatial mappings of a neural‑network layer.
• Open‑source tooling (released with the paper) that lets developers plug in their own layer dimensions and core allocations to obtain runtime estimates instantly.

Methodology

1. Microbenchmarking – The authors run a set of tiny kernels on Loihi 2 to measure:

   • Compute intensity: spikes processed per cycle per core.
   • Communication latency: time to send a packet across varying hop counts.
   • Congestion impact: how packet latency grows with simultaneous traffic.

2. Max‑Affine Modeling – Using the benchmark data, they construct a piecewise linear (max‑affine) surface:

   $$
   T_{\text{pred}} = \max\bigl( \underbrace{a_{\text{comp}} \cdot \text{Ops}}{\text{compute bound}},; \underbrace{a{\text{comm}} \cdot \text{Msgs} + b_{\text{comm}}}_{\text{communication bound}} \bigr)
   $$

   where Ops and Msgs are functions of layer size, sparsity, and core layout.

3. Validation – The model’s predictions are compared against measured runtimes for:

   • A dense matrix‑vector multiply (the linear layer of a neural net).
   • A Quadratic Unconstrained Binary Optimization (QUBO) solver implemented as a spiking network.

4. Scalability Study – By varying the number of cores allocated to a layer, the authors derive analytical expressions that reveal when adding more cores yields diminishing returns due to communication saturation.

Results & Findings

• High predictive fidelity: Correlation coefficients of 0.97–0.99 across test cases, despite the model being a lower bound (i.e., it never over‑estimates runtime).
• Communication dominates beyond modest layer sizes: For dense layers larger than ~2 k neurons, the NoC latency term overtakes compute, leading to linear to super‑linear runtime scaling with layer size.
• Area‑runtime trade‑off: Packing more cores into a compact region reduces hop counts (lower latency) but increases local congestion; spreading cores reduces contention but adds hop latency. The model quantifies the sweet spot for each workload.
• QUBO solver: Even for a highly irregular, sparsely connected problem, the model accurately predicts runtime, demonstrating its applicability beyond standard feed‑forward layers.

Practical Implications

• Algorithm designers can now estimate whether a proposed spiking algorithm will be compute‑ or communication‑bound on Loihi 2 before writing any code, guiding choices such as sparsity patterns or data layout.
• Compiler and mapping tools can incorporate the model to automatically select core allocations that minimize runtime or energy, similar to how roofline models drive tiling decisions on GPUs.
• System architects gain quantitative insight into how scaling the NoC bandwidth or core count would affect overall performance, informing future neuromorphic chip designs.
• Developers building real‑time edge AI (e.g., event‑based vision, low‑latency control) can use the provided open‑source estimator to size their networks to meet strict latency budgets, avoiding costly trial‑and‑error on hardware.

Limitations & Future Work

• The model is a lower bound; it does not capture occasional hardware stalls, thermal throttling, or software overheads (e.g., host‑to‑chip transfers).
• Benchmarks focus on dense linear layers and a single QUBO application; extending validation to recurrent spiking networks, convolutional kernels, or heterogeneous sparsity would broaden confidence.
• Dynamic congestion under highly irregular traffic patterns is approximated with static coefficients; a more detailed queuing‑theoretic extension could improve accuracy for bursty workloads.
• The authors suggest exploring adaptive runtime models that update parameters on‑the‑fly based on observed performance counters, enabling closed‑loop optimization in production systems.

Authors

• Jonathan Timcheck
• Alessandro Pierro
• Sumit Bam Shrestha

Paper Information

• arXiv ID: 2601.10035v1
• Categories: cs.NE
• Published: January 15, 2026
• PDF: Download PDF