What is the timing sequence for Xilinx FPGA to load programs through FLASH?

Source: Dev.to

1. Global power‑up & FPGA initialization

After power is applied, all FPGA supplies ramp (VCCINT, VCCAUX, VCCO_0, etc.).

On POR / configuration restart:

• PROG_B goes low → FPGA clears its configuration memory.
• DONE and INIT_B are driven low.

When the internal memory‑clear finishes, INIT_B is released high (with an external pull‑up), indicating “ready to accept a bitstream”. At that edge the FPGA samples the mode pins M[2:0] and the variant pins VS/FS[2:0] to decide how to configure (SPI vs. BPI, x1 vs. x4, which opcode, etc.).

In many designs the whole “wait for POR + INIT_B high” is required. XAPP951 explicitly says that if the Flash needs > 2 ms to wake, you can hold INIT_B low until then.

Once INIT_B is allowed to go high, the FPGA immediately proceeds to the configuration‑from‑Flash step.

3. Actual configuration from SPI Flash

Now the FPGA is in SPI‑master configuration mode.

Mode pins for SPI

• Virtex‑5 example: M[2:0] = 0 0 1, sampled when INIT_B rises.
• 7‑Series uses a similar encoding (see UG470).

Variant pins VS/FS[2:0]

These pins tell the FPGA which SPI opcode to use, e.g.:

Configuration transaction (simplified)

1. FPGA drives CSO_B / FCS_B low (chip‑select to Flash).
2. FPGA’s internal oscillator generates CCLK, output on the CCLK pin (also clocks the Flash).
3. On MOSI the FPGA sends:
   • 8‑bit READ command (0x03 or 0x0B).
   • 24‑bit start address, usually 0x000000.
   • Required dummy byte(s) if using fast‑read.
4. The Flash responds on MISO → DIN / D_IN, streaming the bitstream bits.
5. The FPGA keeps clocking CCLK and shifting in data until it has received the entire bitstream (recognized by header + sync word + length and CRC).

If the bitstream is valid (CRC OK), the device finishes configuration and moves into startup.

You can estimate the configuration time from the bus width (1/2/4 for SPI, 8/16 for BPI, etc.) as given in the Xilinx documentation.

4. Startup sequence & DONE

After the bitstream is loaded and verified, the FPGA executes an internal startup sequence. A typical (simplified) order—exact order is configurable via bitstream options in UG470—is:

1. Release GSR (global set/reset of flip‑flops).
2. Release GTS (tristate → I/Os become active).
3. Drive DONE high (open‑drain with external pull‑up).
4. Optionally assert EOS (End‑Of‑Startup) inside the fabric.

Key external pin behavior

If a CRC or other error is detected, the FPGA can:

• Drive INIT_B low,
• Abort configuration,
• Optionally fall back / MultiBoot to another Flash address on the next attempt.

5. Putting it all together – textual timing sketch (Master SPI)

Power rails:   ----ramp----> [all above POR] ---------------------------

PROG_B:        ---------L (clear config) ---- H ------------------------>

INIT_B:        L (clear mem) ------H (mode pins sampled) ----- H ------->
               ^ rises when rails are good

M[2:0]/VS[2:0]:       (must be stable BEFORE INIT_B rises) -------------

CSO_B/FCS_B:                           H -----L-----------------H------->
               ^ low during the read transaction

CCLK:                                  idle  clock...clock...  idle ---->

MOSI:                                  cmd  + addr + dummy + ...  ------>

DIN (D_IN):                                   

DONE:        L.............................L..............H(user mode)->

From INIT_B rising to DONE rising is the bitstream‑load + startup time.
If the Flash isn’t ready or the bitstream is corrupt, INIT_B will drop low again and DONE will never go high.

6. Board‑level design tips

When designing or debugging your board:

1. Wait for POR on all FPGA rails.
2. Wait for INIT_B high.
3. Transfer bitstream from Flash (watch CCLK, CS, MOSI, DIN).
4. Watch DONE go high and user logic start.

Oscilloscope‑debug recipe

Probe the following signals: VCCINT, VCCAUX, VCCO_0, INIT_B, CCLK, CSO_B/FCS_B, DIN, DONE.

Confirm:

• INIT_B rises once rails are good.
• FPGA actually toggles CCLK and CS.
• DIN carries data.
• DONE eventually goes high.

If configuration fails

• Verify Flash contents and address (bitstream must be at the address the FPGA assumes, usually 0x0).
• Ensure M[2:0] / VS[2:0] are set correctly for your chosen Flash command and bus width.
• Make sure Flash tPU is fast enough, or gate INIT_B / PROG_B as needed.