TSMC's board approves $45 billion spending package on new fabs — record sign off signals aggressive expansion to grow capacity
Source: Tom’s Hardware
Image credit: TSMC
TSMC’s board approved plans to spend $44.962 billion on building new fabs and upgrading existing production capacities. The approval is part of the company’s broader goal to spend $52 billion–$56 billion on capital expenditures this year, with the remaining funding to be approved at a later meeting. The board also promoted a developer of its 1 nm‑class process technology.
A record spending approval
TSMC holds board meetings each quarter to approve capital appropriations, injections, and dividend distributions. Historically, the company spreads its CapEx approvals relatively evenly throughout the year. For example, in the previous year the board approved:
- Q1: $17.141 billion
- Q2: $15.247 billion
- Q3: $20.657 billion
- Q4: $14.981 billion
The $44.962 billion approval is a record and signals a more aggressive expansion strategy, reflecting the rising cost of advanced fabs.
Capital appropriations are authorizations for management to spend on specific projects; they are not guarantees of actual outlays. Nonetheless, TSMC’s CapEx budgets have been increasing year‑over‑year, and so have the corresponding appropriations.
Earlier this year, TSMC announced plans to allocate 70 %–80 % of its 2026 CapEx to advanced process technologies, 10 %–20 % to advanced packaging and mask making, and roughly 10 % to specialty technologies. Accelerated spending on advanced fabs is intended to keep TSMC ahead of rivals such as Intel and Samsung Foundry in terms of state‑of‑the‑art production capacity, improving its ability to secure large orders.
Promotion of S.S. Lin
During the meeting, S.S. Lin—currently senior director of TSMC’s R&D organization responsible for the A10 (1 nm‑class) process—was promoted to vice‑president. The promotion likely reflects confidence in the progress of the A10 platform and may give Lin broader authority over multiple technology programs, roadmap priorities, and resource allocation.
A10 process technology
The A10 node is TSMC’s post‑A14 fabrication process, expected to become available to customers around 2030 or later. It aims to enable monolithic chips with over 200 billion transistors and may incorporate High‑NA EUV lithography tools.
References