Intel's Make-Or-Break 18A Process Node Debuts For Data Center With 288-Core Xeon 6+ CPU

Source: Slashdot

Overview

Intel has formally unveiled its Xeon 6+ “Clearwater Forest” data‑center processor with up to 288 cores, built on the company’s new Intel 18A process and using Foveros Direct packaging. The chip targets telecom, cloud, and edge‑AI workloads that require massive parallelism, large caches, and high‑bandwidth DDR5‑8000 memory.

Architecture

• Compute chiplets: 12 tiles, each containing 24 energy‑efficient Darkmont cores, manufactured with the 18A node.
• I/O tiles: 2 tiles produced on the Intel 7 process.
• Active base tiles: 3 tiles fabricated on Intel 3.

The compute tiles are stacked on top of the base dies using Intel’s Foveros Direct 3D technology, while lateral connections are enabled by EMIB bridges.

Darkmont Efficiency Cores

The Darkmont cores receive several microarchitectural upgrades:

• 64 KB L1 instruction cache per core.
• Wider fetch and decode pipeline.
• Deeper out‑of‑order engine with increased in‑flight operation tracking.
• More execution ports to boost scalar and vector throughput for heavily threaded server workloads.

Cache Hierarchy

• Cores are grouped into four‑core blocks sharing ~4 MB of L2 cache per block.
• The total last‑level cache exceeds 1 GB, roughly 1,152 MB, providing a large on‑die data pool to keep data close to the hundreds of active cores, reducing external memory bandwidth demand and improving performance and power efficiency.

Platform Specifications

• Drop‑in compatible with the current Xeon server socket.
• 12 memory channels supporting DDR5‑8000.
• 96 PCIe 5.0 lanes, with 64 lanes supporting CXL 2.0.

Source: Tom’s Hardware