[Paper] Automatic Assertion Mining in Assertion-Based Verification: Techniques, Challenges, and Future Directions

Source: arXiv - 2601.02248v1

Overview

Assertion‑Based Verification (ABV) has become the de‑facto method for checking complex hardware designs, but writing high‑quality assertions by hand is time‑consuming and error‑prone. This paper surveys the state‑of‑the‑art automatic assertion miners, compares how they work, and pinpoints where they fall short—offering a roadmap for the next generation of verification tools.

Key Contributions

• Comprehensive taxonomy of modern assertion mining techniques (pattern‑based, machine‑learning‑driven, hybrid, etc.).
• Head‑to‑head benchmark suite that evaluates miners on a common set of RTL designs, measuring coverage, false‑positive rate, and runtime.
• Critical analysis of strengths & weaknesses (e.g., scalability, language support, ability to capture temporal properties).
• Identification of open challenges such as handling multi‑clock domains, integrating with formal solvers, and reducing annotation overhead.
• Future‑direction roadmap outlining promising research avenues (deep‑learning models, incremental mining, cross‑design reuse).

Methodology

1. Literature curation – the authors collected 28 recent miner implementations from conferences, journals, and open‑source repos, focusing on those that are widely adopted in industry or academia.
2. Feature extraction – each miner was broken down into core components (pre‑processing, property inference, post‑processing) and annotated with capabilities (e.g., support for SystemVerilog, ability to infer timing constraints).
3. Benchmark design – a curated set of 12 RTL projects (from simple arithmetic cores to full‑scale SoCs) was compiled, together with a ground‑truth set of manually written assertions.
4. Evaluation metrics – coverage (percentage of ground‑truth assertions recovered), precision (false‑positive ratio), scalability (lines of code vs. runtime), and usability (tool‑chain integration effort).
5. Comparative analysis – results were visualized in heat‑maps and radar charts, and the authors performed a qualitative “pain‑point” survey with verification engineers to validate the numbers.

The methodology is deliberately kept tool‑agnostic so that developers can reproduce the study with their own designs.

Results & Findings

• Hybrid miners consistently delivered the highest coverage while keeping false positives manageable.
• Pure ML approaches excel at discovering non‑obvious temporal relationships but suffer from higher noise and longer training times.
• Formal‑guided miners produce very clean assertions but struggle with scalability on large designs.
• Across the board, multi‑clock and asynchronous domains remain a blind spot; most miners either ignore them or generate overly conservative properties.
• Engineers reported that integration friction (e.g., needing custom scripts to feed RTL into the miner) is a bigger blocker than raw performance.

Practical Implications

• Faster verification cycles – adopting a hybrid miner can cut manual assertion writing effort by ~70 %, letting teams focus on corner‑case debugging.
• Higher defect detection – the increased coverage translates to catching subtle protocol violations that are often missed by hand‑crafted checks.
• Tool‑chain compatibility – the paper’s benchmark suite can serve as a plug‑and‑play validation set for any new miner, helping EDA vendors certify their products.
• Risk mitigation for multi‑clock designs – the identified gaps signal where developers should still rely on manual assertions or complementary formal methods.
• Open‑source starter kit – the authors released scripts to convert common RTL repositories into the benchmark format, enabling teams to evaluate miners on their own IP quickly.

Limitations & Future Work

• The study focuses on SystemVerilog‑based designs; VHDL or mixed‑language projects were not evaluated.
• Ground‑truth assertions were limited to those written by a small group of experts, which may bias coverage numbers.
• Runtime measurements were performed on a single‑node workstation; distributed or cloud‑based mining scenarios remain unexplored.
• Future research directions highlighted include:
  • Deep‑learning models that can ingest hierarchical design information (e.g., block diagrams) to better handle multi‑clock domains.
  • Incremental mining that updates assertions as the design evolves, reducing re‑run costs.
  • Cross‑design knowledge transfer, allowing miners trained on one IP family to bootstrap assertion generation for another.

By shedding light on where current miners excel and where they stumble, this paper equips verification engineers with the knowledge to pick the right tool today—and guides tool developers toward the breakthroughs needed for tomorrow’s hardware complexity.

Authors

• Mohammad Reza Heidari Iman
• Giorgio Di Natale
• Katell Morin-Allory

Paper Information

• arXiv ID: 2601.02248v1
• Categories: cs.SE
• Published: January 5, 2026
• PDF: Download PDF