AMD begins production ramp of 256-core EPYC Venice — first 2nm HPC chip claims 70% performance leap

Source: Tom’s Hardware

Image credit: AMD

Production Ramp Announcement

AMD announced that its 6th Gen EPYC processor, codenamed Venice, has entered production ramp on TSMC’s N2 (2 nm‑class) process technology in Taiwan. The chip packs up to 256 Zen 6 cores and claims a 70 % compute performance gain over the current EPYC Turin lineup, making it the first high‑performance computing product in the industry to reach production on N2. AMD also introduced a follow‑on processor called Verano and said it plans to eventually produce Venice at TSMC’s Arizona campus.

“As AI and agentic workloads scale rapidly, customers need platforms that can move from innovation to production faster,” – Dr. Lisa Su, chair and CEO of AMD.

Technical Specifications

• Socket: New SP7 socket
• Memory: Up to 16 memory channels delivering 1.6 TB/s per‑socket bandwidth
• I/O: Doubled CPU‑to‑GPU bandwidth, indicating PCIe 6.0 support
• Power: Designed for high‑performance workloads with a focus on AI and agentic tasks

These specifications were previewed at AMD’s Advancing AI event last year and at CES in January, and the announcement puts the chip on track for commercial shipments later this year.

Competition Landscape

• Intel’s Diamond Rapids: The P‑core Xeon 7 family, rumored to be delayed to mid‑2027.
• Intel’s Clearwater Forest: An E‑core design built on Intel 18A with up to 288 cores, optimized for high‑density deployments rather than the high single‑thread and general‑purpose performance segment targeted by Venice.

Market Share and Outlook

AMD holds a record 46 % server CPU revenue share as of Q1 2026 (Mercury Research), up from roughly 40 % at the company’s Financial Analyst Day in November 2025. Venice is expected to extend this momentum, especially as Intel continues to rely on its existing Granite Rapids Xeon 6 lineup for at least another year.

Future Production Plans

• Verano: Another 6th Gen EPYC processor built on TSMC 2 nm, optimized for performance‑per‑dollar‑per‑watt.
• Arizona Production: AMD plans to ramp Venice production at TSMC’s Arizona facility (Fab 21 Phase 3), which broke ground in April 2025 and is slated for N2 and A16 processes. Volume 2 nm production at this site isn’t expected before 2028 at the earliest.