Huawei claims sanctions-busting breakthrough with 1.4nm-class chips by 2031, claims 55% higher transistor density — firm claims new LogicFolding chip architecture can bypass EUV restrictions, introduces 'Tau Scaling Law' to replace Moore's Law
Source: Tom’s Hardware
Image credit: Shutterstock
Overview
Huawei announced a new chip design framework aimed at closing the technology gap with global semiconductor leaders such as TSMC and Nvidia. The company targets 1.4 nm‑class transistors and a 55 % increase in transistor density. The announcement was made at the IEEE International Symposium on Circuits and Systems (ISCAS 2026) in Shanghai and is presented as a way to bypass strict U.S. trade sanctions that restrict access to extreme ultraviolet (EUV) lithography machines.
LogicFolding Architecture
During a keynote address, He Tingbo—Huawei board member and President of HiSilicon—unveiled the proprietary LogicFolding architecture, which is built upon the newly introduced Tau Scaling Law. According to Huawei:
- The methodology has been refined over six years.
- 381 chips have already been designed and mass‑produced using this principle.
- The first commercial implementation will appear in flagship Kirin smartphone processors slated for release this autumn.
The LogicFolding architecture physically folds and stacks logic circuits into a dual‑layer framework, drastically shortening internal wiring to eliminate signal delay. Huawei claims this results in:
- 55 % higher transistor density
- 41 % improvement in power efficiency
Tau Scaling Law
The Tau Scaling Law replaces traditional geometric scaling (Moore’s Law) with a temporal scaling approach that prioritizes signal speed over component size. Rather than shrinking transistors, the law focuses on optimizing how fast data moves across a system. By applying this framework, Huawei aims to achieve performance comparable to advanced process nodes without relying on EUV equipment.
Upcoming Kirin Chips
The upcoming Kirin processors—expected in the Huawei Mate 90 series—will be the first commercial chips to feature the LogicFolding architecture. Huawei plans to extend the architecture to:
- Ascend AI processors
- High‑capacity data‑center clusters (targeted for 2030)
By 2031, the company projects it can design high‑end chips with transistor density equivalent to a 1.4 nm process.
Industry Impact
Huawei’s announcement aligns with China’s broader push to reduce dependence on foreign semiconductor players amid ongoing sanctions. The news sparked a 7.6 % surge in shares of SMIC, China’s largest contract chipmaker.
While TSMC aims to mass‑produce true 1.4 nm chips by 2028, Huawei’s alternative path—focusing on chip packaging and structural innovations—could allow China to close the performance gap more rapidly, mitigating the impact of U.S. export restrictions.